1. Field of the Invention
The present invention relates to MOS image sensors, and more particularly to a MOS image sensor capable of taking an image with quality.
2. Description of the Related Art
FIG. 13A is a typical surface view of a CMOS image sensor arranged with a plurality of photodiodes (photoelectric conversion elements) in a square-lattice form on the surface of a semiconductor substrate in an image area thereof. FIG. 13B is a circuit diagram of the same. In a CMOS image sensor 1 illustrated, a multiplicity of unit pixels 3 are arranged in the image area 2. A control-pulse generating circuit 4 and a vertical scanning circuit 5 are formed laterally of the image area 2 while a noise-suppression circuit 6 and a horizontal; scanning circuit 7 are formed in a lower side region of the image area 2.
The unit pixels in FIG. 13A are designated thereon with R, G, B representing red (R), green (G) and blue (B) filters.
The unit pixel 3 is configured with a photodiode 3a (see FIG. 13B) and a signal-read circuit to read out a signal detected by the photodiode 3a (although FIG. 13B shows a signal-read circuit in the related-art four-transistor structure, there are those of three-transistor structures).
On the image area 2 of the CMOS image sensor 1, there are laid lines 10 extending in an X-direction (horizontal) and lines 11 extending in a Y-direction (vertical). The lines 10 are connected to the control-pulse generating circuit 4 and vertical scanning circuit 5 while the lines 11 are connected to the noise-suppression circuit 6 and horizontal scanning circuit 7.
Those lines 10, 11, laid in X- and Y-directions over the image area 2, are referred to as “global lines” in order to distinguish those, say, from the internal lines of the signal-read circuit or of the control-pulse generating circuit 4, vertical scanning circuit 5, noise-suppression circuit 6 and horizontal scanning circuit 7. The global lines include row-select, row-reset, power and output-signal lines, which are generally formed of metal, such as aluminum or copper.
The related-art CMOS image sensor 1 thus structured can be manufactured by use of the general-purpose CMOS process (DRAM process, etc.) differently from the CCD image sensor using an exclusive manufacturing process, hence being considered low in fabrication cost as compared to the CCD image sensor.
This is because that the CMOS image sensor 1 uses, as its photodiodes 3a, part of MOS transistors (PN junctions) fabricated similarly to other CMOS-LSIs wherein the signal-read circuit for reading a signal out of the photodiode 3a also is configured as a combination of a plurality of MOS transistors.
Meanwhile, out of the photodiodes 3a, a photodiode must be selected to read out a signal. Such selection is made feasible by the global lines 10 connected to the signal-read circuits for the respective photodiodes, similarly to the memory selection in the DRAM.
FIG. 14A is a schematic perspective view of the CMOS image sensor in a part covering one unit pixel. FIG. 14A is a typical sectional view of the same.
Visible rays of light 15 externally enter through a microlens (top lens) 16, color filter layer 17, etc. arranged corresponding to the pixel, on a unit-pixel-by-unit-pixel basis, which light arrives at the photodiode 3a. 
On this occasion, the global lines 10, 11 act to block part of the incident light. Part of incident light is multi-reflected at between the global lines 10, 11 or with a metal thin film (shade film, usually an aluminum film) shading the area of the signal-read circuit 18 (see FIG. 14A), etc. except for the photodiode 3a. The multi-reflection light 20, if leaks into the adjacent photodiode 3a, raises a problem of the image-quality deterioration in a pickup image. The photodiode 3a, formed on the semiconductor substrate, is isolated by the device-isolation region 21 from the MOS transistor constituting a signal-read circuit for selecting and amplifying the signal. In the CMOS process, a gate electrode 22, constituting the MOS transistor, is formed between the device-isolation regions 21, over which a planarization protection film 23 is formed. Thereafter, the first wiring layer is formed of metal, e.g. aluminum.
Provided that the first interconnect layer is a global line 10 extending in an X-direction, there is a need to further form a planarized insulation film over the X-directional global line 10 such that the Y-directional global line 11 crosses with the global line 10 in a manner not to cause an electric short to each other, on which the Y-directional global line 11 is formed.
Usually, a planarization film is further overlaid to form a shade film 19. Furthermore, a planarization film is overlaid to form a color-filter layer 17 thereon. In this manner, in the CMOS process, the global line is usually formed in a multi-level structure.
It is the related-art practice to use a low-resistance metal material, such as Al (aluminum), in order to assure the high-speed operation of the integrated circuit (IC). However, because aluminum has a high on-surface reflectivity, it is difficult to avoid the problem of multi-reflection noted above.
Incidentally, the prior arts concerning CMOS image sensors include, say, a description in JP-A-2001-298176.
Image sensors include those having photodiodes in a matrix arrangement wherein the photodiodes on the even row are arranged deviated a half pitch relative to the photodiodes on the odd row as described in the below JP-A-10-136391, besides the image sensors arranged with photodiodes in a square lattice form on the image area. This arrangement, i.e. so-called honeycomb arrangement, has already been realized on the CCD image sensor wherein the vertical transfer line, provided between horizontally (X-directionally) adjacent photodiodes, is formed horizontally (Y-directionally) and zigzag.
There is a desire for realizing a MOS image sensor having photodiodes in a honeycomb arrangement. There are proposals on those described in the below JP-A-5-44642 and JP-A-4-31231. In this case, the global lines 10, 11 also must be formed zigzag in a manner avoiding the photodiodes, similarly to the zigzag vertical transfer line on the CCD image sensor. This increases the length of the line and hence the resistance-through-the-line. Besides, there is a need to resolve the problem of image-quality deterioration due to multi-reflection noted before.
The MOS image sensor is formed with a multi-level structure of wiring layers over a semiconductor substrate formed with photodiodes and signal-read circuits, over which an optical layer, such as of a color filter and a microlens, are formed structurally. Along with the recent advancement of micro-fabrication technology, the number (density) of pixels increases for the image sensor, resulting in the tendency toward decreasing the opening dimension of one pixel and the distance to the adjacent pixel. However, there is no advancement of miniaturization in the height direction. In each pixel, the optical path is becoming narrower for the incident light traveling from the microlens to the photodiode. Thus, as the number of pixels increases for the image sensor, there is an increasing effect of multi-reflection that is not to be ignored.
Where providing photodiodes in a honeycomb arrangement for the MOS image sensor, the global lines must be devised for taking a quality image while preventing the multi-reflection of incident light. Meanwhile, attentions must be paid not to cause a trouble in reading a signal or supplying power through the global lines.